PC2-5300 / DDR2-667 240 Pin DDR2 Unbuffered DIMM
Capacity Chip Configuration Chip Type
Non-ECC With ECC
256MB 32Mx16 (x4) 32Mx16(x5) DDRII SDRAM
512MB 64Mx8 (x8) 64Mx8(x9) DDRII SDRAM
1GB 64Mx8(x16) 64Mx8(x18) DDRII SDRAM
2GB 128Mx8(x16) 128Mx8(x18) DDRII SDRAM

240 edge connector pads
Data Rate 667 MHz
SSTL-18 interface 1.8 Voltage +/- 0.1V
Package FBGA

JEDEC Standard
Bandwidth(max): 5.3GB/s
Date Rate: 667MHz
Double Data Rate architecture
Differential Data Strobe (DQS)
Differential clock inputs (CK and /CK)
MRS cycle with address key programs
* CAS latency: 3, 4& 5
* Burst length: 4 & 8
* Burst type: Nibble Sequential & Interleave

2 variations of refresh
*Auto refresh & Self refresh

Edge aligned data output, center aligned data input
2 banks to be operated simultaneously or independently
Serial Presence Detect with EEPROM